Semiconductor devices, in particular high power semiconductor devices, require an efficient edge termination to avoid electric field crowding at the edge of the main contact resulting in breakdown of the device at a relatively low breakdown voltage VBR. Common power semiconductor devices, such as a pin diode or an insulated-gate bipolar transistor (IGBT), require a means of planar edge termination in order to achieve a breakdown voltage in the range of 80 to 90% of the ideal one-dimensional diode breakdown voltage.
For silicon-based devices known planar edge termination techniques include junction termination extension (JTE), variation of lateral doping (VLD) and floating field ring terminations (FFR) with and without field plate extensions. Etched and refilled trenches have also been used. Silicon carbide (SiC) and especially 4H-SiC is an attractive material for high power semiconductor devices due to its ten times higher critical electrical field than that of silicon. Given the well-known restrictions with SiC process technology, there are significant constraints for forming planar edge terminations in SiC-based high power semiconductor devices. For example, when planar junctions are to be formed in SiC by implantation the junction depth is limited to about 2 μm.
Floating field rings and the junction termination extension are the most commonly used edge termination techniques in 4H-SiC based high power devices. The floating field ring termination structure has the advantage that the generation of floating field rings can be easily integrated in the manufacturing process since the floating field rings can be formed simultaneously with a main junction. Accordingly, it is possible to form the floating field rings without having to increase the necessary number of masks. On the other hand, the design of a high performance floating field ring termination is very challenging given the high number of factors affecting the most important trade-off between breakdown voltage and occupied wafer area. This trade-off is strongly affected by interface trapped charges (technology impact) and by design parameters, such as the lateral width and depth of the floating field rings or the distance between two neighbouring floating field rings.
The purpose of the floating field ring termination structure is to alleviate the field crowding effect at the outer edges of the device main junction by allowing the depletion region to extend through consecutively lower biased floating junctions. To be effective, the distances between these floating field rings as well as their width in the lateral direction have to be thoroughly optimized to achieve an even distribution of the electric field. In addition, the effect of the floating field ring termination structure is very sensitive to the influence of parasitic surface charges which inherently result from the processing conditions during the manufacturing process for a high power semiconductor device.
Floating field ring termination systems are in use for low and medium voltage components (600 V to 3.3 kV IGBTs, for example). For these voltage classes, appropriate breakdown voltages can be achieved with 3 to 15 floating field rings. For even higher voltages, the number of floating field rings required to reach 6 to 10 kV blocking capability will reach 30 to 50 resulting in a reduced wafer area being available for the active area. To attain a high current handling capability the active area should be as large as possible. Therefore, the area efficiency of a planar edge termination structure is of utmost importance for the current handling capability of a high power semiconductor device having a planar edge termination structure. Due to the high number of required floating rings this a particular critical aspect especially for high voltage devices employing a floating field ring structure.
In prior art document U.S. Pat. No. 5,075,739 A there is described a high voltage planar edge termination structure comprising a plurality of guard rings. To increase the punch-trough breakdown voltage between the guard rings there is provided an enhancement region formed in the separation region between two neighbouring guard rings which connects these two neighbouring guard rings with each other, respectively. The enhancement region has a conductivity type which is different from that of the guard rings and has a doping concentration higher than that of the semiconductor substrate in which the guard rings are formed. The enhancement region allows two neighbouring guard rings to be disposed more close to each other and to thereby improve the area efficiency.
From the prior art document U.S. Pat. No. 6,445,054 B1 there is known a high power semiconductor device having a planar edge termination structure comprising p+ floating rings formed in an n− drift layer, the p+ floating rings surrounding an active area of the high power semiconductor device. The floating field rings are formed just below a passivation layer in the form of a surface field oxide layer. Respective additional n and p shallow rings are formed on opposite sides of each one of the main p+ floating rings to overcome the problem of severe deterioration of the device's breakdown characteristic, when there was either negative or positive charge in the surface field oxide layer. The additional n and p shallow rings have a lower doping concentration than that of the p+ floating rings, but have a higher doping concentration than that of the n− drift layer.
From the prior art document US 2014/252553 A1 there is known a MOSFET having a p-base layer, floating field rings covered with a field oxide layer and an n-drift layer. The floating field rings are embedded in a lowly or non-doped layer.